1. Field of the Invention
The present invention relates to a semiconductor memory apparatus and a method of manufacturing the same, and more particularly to a memory cell array structure of ROMs (Read Only Memory) for storing multi-value level data.
2. Description of the Related Art
In a conventional ROM memory cell array which is a general read-only semiconductor memory apparatus, memory cells comprising MOS FETs are arranged in a matrix. The gates of the memory cells are connected to a plurality of word lines extending in the row direction, and the sources and drains are connected to a plurality of bit lines extending in the column direction. In this structure, the capacity of the array is increased and the number of memory cells connected to the bit lines increases. Accordingly, a parasitic capacitance of the bit lines increases and read-out speed decreases. There has been proposed a bank-type ROM in which the parasitic capacity of the bit lines is decreased and the read-out speed is improved. In this ROM, the bit lines comprise main bit lines with a longer wiring length and sub-bit lines with a less wiring length. The memory cells are stored in a plurality of banks, and the sub-bit lines are connected to memory cells of the banks. The main bit lines are connected to sub-bit lines via selection transistors. In this ROM memory array having this structure, a predetermined memory cell is read out in the following manner. The selection transistor is operated on the basis of a bank selection signal representing the bank to be selected, to which the predetermined memory cell belongs. Thereby, the sub-bit line is electrically connected to the main bit line.
The word line connected to the gate of the predetermined memory cell is set at high level and the data in the predetermined memory cell is read out. Since the operation is effected in the state in which the sub-bit line of the bank is electrically connected to the main bit line and the junction capacitance of the memory cells of each column is divided, an operation delay can be prevented effectively. In a ROM, a one-bit memory is normally composed of one transistor. In order to set data in each memory cell, a threshold voltage of the memory cell set in two levels, a high level and a low level. Even if the data is set in this manner, only one-bit data can be stored in one memory cell. Thus, in order to fabricate a large-capacity memory, the chip size increases disadvantageously.
In order to solve this problem, a method has been proposed wherein two-bit data is stored in one memory cell and thereby the chip size is reduced. A ROM employing this method is called "multi-value ROM." According to this method, a gate length or a gate width of a transistor of a memory cell is varied to set a plurality of different current values, or an implantation amount is varied to set a threshold voltage at a plurality of levels. In this description, the method in which the threshold voltage is varied will be explained.
FIG. 1 shows a conventional bank-type ROM and more particularly it is a plan view of a memory cell array formed on a semiconductor substrate 10 by using an imaginary ground method. Main bit lines 1 and main imaginary ground lines 2 arranged alternately on the semiconductor substrate 10 are made of aluminum, and sub-bit lines 3 and sub-ground lines 4 are formed of an N.sup.+ diffusion layer on a surface region of the semiconductor substrate. Thus, these lines have a bit line multi-layer structure. Word lines 5 and bank selection lines 6 crossing the main bit lines and main imaginary ground lines are formed of a polycide layer. Memory transistors 7 are formed such that their sources and drains are formed of intersection portions between the N.sup.+ diffusion layer and polycide layer. A memory cell array, which comprises bank selection transistors 8 connected to the sub-bit lines at one end and the memory transistors 7 having gates connected to 32 gate lines, is divided in units of a bank along the bit lines. The divided sub-bit line is connected to the main bit line via the bank selection transistor. The main imaginary ground line is connected via the bank selection transistor to the sub-ground line to which the source of the memory cell transistor is connected. The main bit line and main imaginary ground line are arranged adjacent to each other. In this prior-art example, four banks constitute one memory cell array. In this way, the device section of the ROM consists of a plurality of memory cells, and a plurality of memory cells are arranged in a matrix.
FIG. 2 is a cross-sectional view of the memory transistor 7 formed in a device region of a surface portion of the silicon semiconductor substrate used in the ROM. A source region 11 and a drain region 12 are formed in the surface portion of the semiconductor substrate 10 such that the source region 11 and drain region 12 are situated apart from each other. A gate 9 is formed above a portion of the semiconductor substrate 10 between both regions, with a gate oxide film (not shown) interposed. The gate 9 is made of a polycide having such a structure that a silicide such as tungsten silicide is formed on a polysilicon. The gate 9 is continuous with the gates of other adjacent memory transistors, thereby forming the word line 5 shown in FIG. 1. If necessary, ions are implanted in the portion between the source and drain regions 11 and 12 below the gate 9, thereby controlling the threshold value of the transistor. In this example, four different thresholds are set. After the polysilicon gate 9 is formed, the threshold control ion implantation ("ROM implantation"), i.e. channel implantation, is performed through the polysilicon gate 9, thereby varying the threshold voltage of the memory cell. In this case, if the channel implantation is not performed, another threshold value is set. Thus, if the channel implantation is not performed, four threshold voltages are obtained by selecting the implantation amount among implantation amount 1, implantation amount 2 and implantation 3 (implantation amount 1&gt;implantation amount 2&gt;implantation amount 3).
FIG. 3 is a current/voltage (Id--Vg) characteristic graph showing a relationship between the threshold voltage of the memory cell and the drain current. The right portion of FIG. 3 shows stored data items corresponding to the threshold values. The threshold voltage Vth is set, e.g. at one of four threshold voltage values, Vth1 to Vth4, as shown in FIG. 3, in accordance with two-bit data D0, D1 stored in the memory cell. Specifically, if the ROM implantation corresponding to the threshold voltage Vth2 is performed, data "0" is output in accordance with address D0 and data "1" is output in accordance with address D1. Reference levels (Ref1, Ref2, Ref3) are set at intermediate levels of potentials set by the threshold voltages Vth1, Vth2, Vth3 and Vth4 when the gate voltage (Vg) of the memory cell is 5 V. In order to detect the multi-value data of the memory cell, a reference voltage output from a reference voltage generating circuit is input to a sense amplifier, and the threshold voltage vth input to the amplifier is compared with the reference voltage. A comparison result is input to a logical circuit. Data items corresponding to the two addresses D0 and D1 are read out from the logical circuit. Thereby, two-bit data can be read out from the one-bit memory cell, and double-amount data can be stored in the memory cell having the same size as a conventional one. In other words, with the same memory capacity as prior art, the chip size can be greatly reduced. If the multi-value memory cells are used, the memory cell area can be reduced remarkably.
FIG. 4 shows the structure of an equivalent circuit of the imaginary ground type cell array shown in FIG. 1. With reference to FIG. 4, the read-out of the memory cell will now be described.
A plurality of main bit lines (BL) and a plurality of main imaginary ground lines (GL) are alternately arranged in columns. One end of each of both lines is connected to a bias circuit. 32 word lines (WL) are arranged in the row direction so as to cross these lines. Two bank selection lines (SL) are arranged on each of both sides the 32 word lines (WL). The bank selection line SL1 is connected to the bank selection line SL3 to have the same potential, and the bank selection line SL2 is connected to the bank selection line SL4 to have the same potential. The main bit lines and main imaginary ground lines are connected to three sub-bit lines and three sub-ground lines via selection transistors (ST). The selection transistors have their gates connected to the bank selection lines. For example, the selection transistor ST1 is connected to the bank selection line SL4, and the selection transistors ST2 and ST3 are connected to the bank selection line SL3. The memory transistors are connected to the word lines, sub-ground lines and sub-bit lines. Numbers are added to 16 memory transistors connected to the word line WL1, and these are called cell 1, cell 2 . . . , cell 16.
Of the main bit lines BL1 to BL4 and main imaginary ground lines GL1 to GL4, the line GL2 is set at the ground level, i.e, Vss and the line BL2 is connected to the sense amplifier. The line BL3 is set in the floating state. The other main bit lines (BL1 and BL4) and the other main imaginary ground lines (GL1, GL3 and GL4) are biased. If the latter bit lines and ground lines are not biased, a leak current flows to the cells 10 to 14 as with the case of "1" cell (data "1"), as shown in FIG. 9 (this leak current is indicated by symbol A). The leak current can be prevented by the bias circuit. In addition, when the cell adjacent to the selected cell is a "1" cell, the unnecessary N.sup.+ diffusion layer and bit lines are charged to decrease the read operation speed. The above biasing of the bit lines and ground lines avoids this problem by previously charging these lines to increase the read operation speed. When the cell 7, for example, is to be read out, the line SL2 is set at high level to connect the drain of the cell 7 to the line BL2 and the line SL4 is also set at high level to connect the source of the cell 7 to the line GL2. At the same time, the word line WL1 of the 32 word lines WL1 to WL32 is set at high level, the drain of the cell 7 is connected to the sense amplifier via the main bit line SL2. In accordance with the data of the cell 7, the sense amplifier senses "1" or "0".
In the case of the conventional cell array type memory, when the cell 6 is the "1" cell, bias is effected, as shown in FIG. 5. Thus, a leak current B flows. Consequently, a current flowing to the drain increases and the drain voltage rises. When the cells 10 and 11 are "1" cells, a leak current C flows. Furthermore, when the cells 8, 9, 10 and 11 are "1" cells, a leak current D flows. Consequently, since a current Icell flowing to the source of the cell increases, the source potential of the cell rises due to the voltage drop. Accordingly, the current Icell decreases and the drain potential increases. In any case, the leak current acts to raise the drain voltage of the cell. Thus, as compared to the case where the leak path is not provided as shown in FIG. 7, the output potential (Vdatin) of the cell increases. FIG. 6 shows an example of a leak path which is produced when the leak is not due to the bias. Through this leak path, a leak current E flows when the cells 8 and 9 are "1" cells and the cell 10 is the "0" cell (data "0"). In this case, since the current Icell increases apparently by the amount corresponding to the leak current, the drain potential decreases.
Accordingly, as shown in FIG. 7, the output (Vdatin) of the cell decreases. In this type of cell array, since the current flowing into the source and drain of the cell varies depending on the state of the surrounding cells, the values of the output potential Vdatin and the current Icell of the cell vary. FIG. 7 is a characteristic graph showing bias-dependency of the output potential. If leak currents B to E flow, an output potential characteristic curve departs greatly from an ideal one shown by a solid line. If output potentials Vdatin are Vdatin1, Vdain2, Vdain3 and Vdain4, when the threshold voltages vth of the cell are vth1, Vth2, vth3 and vth4, these potentials Vdain due to leak vary as shown in FIG. 8. If the multi-value ROM is realized by this cell array, a margin decreases and practicability lowers. In this bank-type multi-value ROM, the cell arrays are separated by implantation for setting a high threshold value vth. In this case, the threshold voltage Vth is about 5 V at most because of a problem of leak. According to this system, if the gate voltage is raised 5 V or more, the conductivity type of the separation region formed by the high-concentration implantation is reversed and the device is turned on. As a result, a cell array current flows. In addition, if four threshold voltages Vth are to be provided in fabricating the multi-value ROM, four or three masks are required and the manufacturing process is complicated.